1. Field of the Invention
The present invention relates to digital phase-locked-loop (PLL) devices that are mounted, for example, on disc drive apparatuses.
2. Description of the Related Art
Digital PLL systems are used in data recording/playback apparatuses such as disc drive apparatuses, as disclosed, for example, in Japanese Unexamined Patent Application Publication No. 11-341306 and Japanese Unexamined Patent Application Publication No. 9-247137. When playback information (i.e., playback RF signal) is read from a disc or the like, a clock that is synchronized with the playback information is generated using a PLL circuit, and data representing the playback information is extracted using the clock.
As an example, FIG. 79 shows an example system configuration for data extraction by digital PLL in a disc playback apparatus for compact discs (CDs) or digital versatile discs (DVDs).
The digital PLL system shown in FIG. 79 receives input of playback RF signal generated based on reflected light detected by an optical head of the disc playback apparatus, and generates run-length data that serves as playback information from the playback RF signal.
The RF signal is input to an asymmetry correcting circuit 61 and is binarized therein. The RF signal binarized in the asymmetry correcting circuit 61 is supplied to a master PLL control circuit 65. The master PLL control circuit 65 generates a reference clock having the same frequency as 1T of the RF signal from the binarized RF signal, and outputs the reference clock to a voltage-controlled-oscillator (VCO) control circuit 66.
The VCO control circuit 66 controls a VCO 67 so that the oscillation frequency of the VCO 67 will be the same as the frequency of the reference clock. Under the control of the VCO control circuit 66, the VCO 67 outputs a clock (hereinafter referred to as a high-frequency clock) by oscillation.
A frequency control circuit 68 receives the binarized RF signal and the high-frequency clock from the VCO 67. The frequency control circuit 68 samples the binarized RF signal using the high-frequency clock, and detects a deviation between the frequency of the RF signal and the oscillation frequency of the VCO 67.
A phase control and run-length determining circuit 62 receives the binarized RF signal, the high-frequency clock from the VCO 67, and a signal representing a frequency deviation from the frequency control circuit 68. The phase control and run-length determining circuit 62 generates a channel clock synchronized with the RF signal using the signal representing the frequency deviation and the binarized RF signal, and extracts run-length data from the RF signal using the channel clock. The phase control and run-length determining circuit 62 also outputs a phase error.
The extracted run-length data and the phase error are supplied to a run-length correcting circuit (hereinafter also referred to as an RLL circuit) 63. The RLL circuit 63 corrects run-length data based on the run-length data and an associated phase error. Run-length data that has been corrected is supplied to subsequent decoding circuitry that is not shown, and is decoded therein.
The phase error is also supplied to a jitter meter 64. The jitter meter 64 measures a jitter value using the phase error.
Furthermore, the run-length data from the phase control and run-length determining circuit 62 are also supplied to the master PLL control circuit 65.
The conventional digital PLL system described above has had various problems described below.
<Problems of the Asymmetry Correcting Circuit 61>
In the asymmetry correcting circuit 61 where binarization is executed, it is essential to maintain an appropriate level of a signal for slicing analog RF signals. In some cases, however, it is not possible to maintain an appropriate slice level due to a disturbance superposed on a desired signal. Factors that could cause such a disturbance include nature of the signal source, characteristics of the system, noise on the transmission system, damage or dirt on a physical recording medium such as a disc medium, and physical factors such as vibration.
Conventionally, in order to correct asymmetry of an RF signal, a system that feeds back an average value of an input signal (RF signal) and uses it as a slice level has been implemented by an analog circuit. For example, referring to FIG. 80, an RF signal is input to a comparator 71 via a capacitor C and resistors R1 and R2. The comparator 71 performs comparison based on a slice level supplied from an amp 73, and outputs a binarized RF signal. The binarized RF signal is averaged by a low-pass filter 72, and a resulting slice level is input to the comparator 71 via the amp 73.
This arrangement is feasible in cases where the quality of the input signal (RF signal) is favorable. However, when the level of the input signal is deviated due to a disturbance or the like, since the nature of the disturbance is not known, it has been difficult to perform appropriate correction depending on the deviation by the analog circuit on the spot.
Furthermore, it is also possible that the speed of signals considerably varies within a single system. This implies that the response speed of the circuit must be controlled in accordance with the signal speed even in cases of the same type of disturbance. Practically, it is difficult to implement a system that handles disturbance by an analog circuit. Thus, effective measures have not been taken against various types of asymmetry deviation.
<Problems of the VCO 67 and the VCO Control Circuit 66>
A conventional VCO has only one control terminal. FIG. 81 shows change in oscillation frequency in relation to control voltage in the conventional VCO. In FIG. 81, the horizontal axis represents the control voltage, and the vertical axis represents the oscillation frequency. A VCO must be capable of oscillating at any frequency in accordance with the control voltage in a range of VDD to VSS, as shown in FIG. 81. However, in this VCO, the frequency changes greatly in relation to change in the control voltage. The change in frequency in relation to the change in the control voltage is represented by Δf1/ΔV in FIG. 81.
The fact that the frequency changes greatly in relation to the change in the control voltage implies that even a slight change in the control voltage caused by noise or the like results in a considerably change in the frequency. This significantly affects the playability (performance) of the circuit.
As a countermeasure, it is possible to improve susceptibility to noise by increasing the time constant of the low-pass filter in relation to the control voltage so that slight variation of the control voltage will be suppressed. This approach, however, degrades tracking characteristics.
In order to lock a PLL while not increasing jitter, the change in the oscillation frequency in relation to the change in the VCO control voltage must be gradual.
An approach for achieving this is to prepare VCOs optimal for respective frequency bands and to use the VCOs by switching. As an example, FIG. 82 shows a case where four VCOs VCO-A, VCO-B, VCO-C, and VCO-D are used.
In FIG. 82, (a), (b), (c), and (d) represent frequency characteristics of the VCO-A, VCO-B, VCO-C, and VCO-D, respectively. In FIG. 82, the horizontal axis represents the control voltage, and the vertical axis represents the oscillation frequency.
As will be understood from FIG. 82, the change in the frequency in relation to change in the control voltage (Δf2/ΔV in FIG. 82) is more gradual than in the case shown in FIG. 81 (Δf1/ΔV).
According to the arrangement using a plurality of VCOs, however, switching among the VCOs is needed each time the playback speed of disc medium is changed. This inhibits seamless tracking.
In the example shown in FIG. 82, when the oscillation frequency is changed from 100 MHz to 200 MHz, i.e., from point (e) to point (f), switching from the VCO-A to the VCO-B must take place, so that tracking characteristics are degraded.
Furthermore, in the conventional circuit shown in FIG. 79, the length of an RF signal is measured in the frequency control circuit 68 and the phase control and run-length determining circuit 62, using a high-frequency clock generated by the VCO 67. Therefore, a deviation in the oscillation frequency of the VCO 67 results in inaccurate measurement of the length of an RF signal. This significantly affects playability. It is desired that the change in the oscillation frequency of the VCO 67 in relation to the control voltage is linear (i.e., Δf1/ΔV is constant), as shown in FIG. 81. Actually, however, the change in the oscillation frequency of a VCO in relation to the control voltage is not linear due to circuit configuration or process variation, as shown in FIG. 83. Thus, the gradient is small in some parts as denoted by Δf3/ΔV, and large in other parts as denoted by Δf4/ΔV.
When the gradient is large as denoted by Δf4/ΔV, noise superposed on the control voltage causes a considerable deviation of the oscillation frequency.
Conventionally, digital circuits have not been used as counter measures against the non-linearity of the frequency characteristics of VCOs.
<Problems of the Frequency Control Circuit 68>
The oscillation frequency of the VCO 67 is controlled by the master PLL control circuit 65 and the VCO control circuit 66 so as to coincide with the frequency of 1T of an RF signal (4.3218 MHz×n in the case of a CD, and 26.16 MHz×n in the case of a DVD).
However, immediately after movement of the disc is started, or in the case of a disc having eccentricity, a frequency deviation temporarily occurs between the frequency of an RF signal and the oscillation frequency of the VCO 67. Two types of such frequency deviation exist.
One is a case where the playback speed of the disc considerably changes, for example, when rotation of the disc is started or when a long track jump occurs. In this case, the frequency of the RF signal and the frequency of the VCO must be brought into a locked state where the frequencies are matched from an unlocked state where the frequencies are not matched.
The other type is caused by fluctuation of a spindle motor that rotates the disc. In the case of a disc having eccentricity, the frequency of the RF signal is matched with the frequency of the VCO at first, and a frequency deviation occurs as the frequency of the RF signal gradually changes. In the case of he fluctuation of the spindle motor, wow and flutter of motor control affects the length of the RF signal, whereby a frequency deviation occurs.
These types of frequency deviation can be handled by a wide capture range and lock range of a PLL system, whereby favorable tracking characteristics are achieved.
When a frequency deviation has occurred as described above, the frequency deviation must be detected in some way. Conventionally, the frequency deviation has been detected using only pulse-length data of a binarized RF signal measured using a high-frequency clock.
However, for example, if the pulse length is 10.5T, it is not possible to determine whether the pulse length is actually 10T but incorrectly measured to be longer, or the pulse length is actually 11T but is incorrectly measured to be shorter. Thus, a pulse-length that cannot be determined must be considered as falling in an insensitive region.
FIGS. 84A and 84B show effect of difference of pulse-length data with the same frequency deviation. In FIG. 84A, the pulse length is measured as 5.25T, so that it is possible to determine that the pulse length is actually 5T but is incorrectly measured to be longer. On the other hand, in FIG. 84B, the pulse length is measured as 10.5T, so that it is not possible to determine from the pulse-length data alone whether the pulse length is actually 10T but is incorrectly measured to be longer or the pulse length is actually 11T but is incorrectly measured to be shorter.
As shown in FIG. 84, a frequency deviation considerably affects pulse length data of a long pulse length, so that long pulse-length data must have a larger insensitive region.
However, an increase in insensitive region reduces the number of pulse-length data in which a frequency deviation can be recognized. This results in slower recognition of a frequency deviation.
Furthermore, in order to increase the range of frequency deviation that can be detected, short pulse-length data that can be recognized even under the influence of a frequency deviation must be used. As shown in FIG. 85, an RF signal is an analog signal having a certain gradation, and the amplitude thereof varies depending on pulse-length data. Short pulse-length data corresponds to a small amplitude of an RF signal, so that it is susceptible to disturbance such as a jitter and is therefore not so reliable. Thus, the reliability of a calculated frequency deviation is low.
<Problems of the Phase Control and Run-Length Determining Circuit 62>
In the case of playback by the related art, a channel clock that is synchronized with a binarized RF signal is generated by a digital PLL. In FIG. 19, part (a) shows the binarized RF signal, part (b) shows the channel clock, and part (c) shows an RF signal sampled based no the channel clock. In the digital PLL, in order to match the phases and frequencies of the RF signal and the channel clock, a high-frequency clock (Hif) is divided by 7.5, 8.0, and 8.5 while also using reverse edges of the high-frequency clock, and the phase is advanced or delayed, whereby the channel clock is generated.
For example, the operating frequency of the digital PLL for playing back a DVD at the speed of ×1 is 209.28 MHz, which is eight times the frequency 26.16 MHz of the channel clock needed for the speed of the DVD. The operating frequency of the digital PLL for playing back a DVD at the speed of ×20 is 4.185 GHz, which is twenty times the frequency 209.28 MHz. It is difficult to achieve a frequency higher than 4 GHz by the current CMOS process. Even if that is possible, power consumption is increased due to high-speed operation, the lifetime of LSIs is decreased, or LSIs not satisfying specifications are manufactured and yield is decreased.
As another method of improving playability using known techniques, it is also possible to increase the resolution of the channel clock. This approach, however, further increases the frequency of the high-frequency clock, and is therefore infeasible for high-speed playback.
<RLL Circuit 63>
When a CD or a DVD is played back, run-length data that is impossible to occur is sometimes read, due to noise or damage on the disc, or rough manufacturing of the disc itself.
In the conventional RLL circuit 63, with regard to data whose inversion interval is supposed to fall within a range of 3T to 1T, only data that is shorter than 3T, i.e., the minimum inversion interval, is corrected. The method of correction is determined based on the length of previous or subsequent run-length data, or the magnitude of a phase error. That is, run-length data that is shorter than 3T is removed or extended (for example, 2T is impossible, so that 2T is extended to the minimum inversion interval of 3T) according to a simple rule, and the correction is not based on an examination as to how the run-length data is actually broken.
Furthermore, correction of successive run-length data that is against a predefined format is not considered at all. Therefore, the reliability of correction is low.
Furthermore, run-length data that exceeds 11T is not corrected, so that the correction has no effect on such data.
Furthermore, sync patterns are not considered, and it is possible that false sync patterns are generated by the correction. This could degrade playability.
<Problems of the Jitter Meter 64>
The conventional jitter meter 64 obtains a jitter value by accumulating the presence or absence of a phase error measured by a high frequency clock, that is, whether the phase error is zero or not. This is because accumulation of binary values is difficult since the operating frequency high even when the playback speed of a disc is low. The conventional jitter meter 64 is not capable of measuring a jitter at a speed of ×8 of a CD or ×1.6 of a DVD.
Furthermore, a phase error is not used as it is, but is replaced by a simple signal representing the presence or absence of error. Thus, it is not possible to find correlation between jitter values measured by a measurement device available on the market and data output by the jitter meter 64.